Design Verification Engineer

Design Verification Engineer

Experience : 5+ Years

Salary Range :SGD 7000-10000

Skills Required:

FPGA SoC Verification Skills

ASIC SoC Verification Skills

System Verilog and UVM Skills

Automation Skills .

IP Verification Skills

Low power UPF based verification skills

Technical Expertise

Languages :Verilog, System Verilog, C, C++.

Verification Methodologies:UVM, OVM.

Scripting Languages:Perl,C-shell.

Simulators:Cadence IUS, Synopsys VCS, Verdi.

Protocols:PCIe,AGPT,CFDM,SPI,ISO7816,

DDR3, LPDDR2, GPIO, AXI, AHB, APB, JTAG, WDT, GPT.