Espressif is looking for a Verification Engineer to join our growing and dynamic team. In this role, you will be responsible for developing block, subsystem and system level RTL verification platforms to ensure ICs meet specified requirements.
Job Description
- Use UVM/SV to develop unit tests and integration test platform and define the verification cases according to algorithm/RTL design specification;
- Use Perl/Shell/Python XML to design/simulation environment automation and improve verification efficiency
- Work with algorithm/RTL engineer to generate RM (reference model) and test cases to make sure the bit-true implementation;
- Generate and analyse the code and functional coverage report;
- Work with algorithm and RTL design engineers to find and fix any design defects;
Basic Requirements:
- Bachelor's degree, or above, in Computer Engineering/Electronic Engineering/Communications Engineering, or other related disciplines;
- Familiarity with UVM, Verilog, System Verilog, C and Matlab;
- Proficiency in Perl/Shell/Python scripts;
- Proactive work attitude, good team player, attentive to details and quality
