NPU ASIC IC Design Engineer Entry-Level

RESPONSIBILITIES INCLUDE, BUT ARE NOT LIMITED TO:

• Develop HW microarchitecture, RTL design and verification for Expedera AI accelerators (Silicon IP)
• Explore HW design space power/performance/area optimization
• Collaborate with HW/SW architects in HW/SW co-design
• Execute with DevOps for quality assurance

REQUIRED QUALIFICATIONS AND EXPERIENCE:

• Bachelor's degree or equivalent in a relevant field such as electrical engineering, computer science
• Graduating Masters are welcome
• Familiarity with Verilog, Python, Linux

PREFERRED QUALIFICATIONS AND EXPERIENCE:

• SystemVerilog, Univeral Verification Methodology
• C++
• Git, Jenkins, Continuous Integration/Continuous Delivery, JIRA
• Machine Learning/Deep Learning
• GPUs, AI accelerators/NPUs, FPGAs