Responsibilities:
- Algorithm Implementation: Translate complex ISP algorithms into efficient hardware designs using Verilog, SystemVerilog, and/or SystemC (HLS).
- Architecture Definition: Develop robust ISP hardware architectures that meet stringent performance, power, and area constraints.
- Design Verification: Rigorously verify ISP logic and digital system-level functionality.
- Optimization: Employ advanced optimization techniques to minimize gate count and power consumption.
- Cross-Functional Collaboration: Lead and coordinate with ISP algorithm teams, global design teams, and digital system design teams.
- Team Leadership: Mentor and guide a talented team of RTL design engineers.
Requirements:
- Technical Expertise: Master or Degree in Electrical Engineering or equivalent, coupled with 7+ years of hands-on digital design and verification experience.
- Leadership Skills: Proven track record in leading and managing teams, demonstrated by 3+ years of project and people management experience.
- Domain Knowledge: Deep understanding of CMOS image sensors and image signal processing (ISP) principles.
- Design Tools Proficiency: Expertise in SystemC/C++, SystemVerilog, and Catapult HLS tools.
- Interpersonal Skills: Strong communication and interpersonal abilities to effectively collaborate with diverse teams.
- Time Management: Excellent time management skills to ensure timely delivery of high-quality results.
- Adaptability: A proactive and results-oriented mindset, capable of embracing change and driving innovation.
- Language Proficiency: Fluency in Chinese to facilitate seamless communication with stakeholders in China.
Interested candidates kindly click the APPLY NOW button.
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EnviroDynamics Solutions Pte Ltd
Reg. No: R1324803
EA License No.: 12C6285
