110

Asic Jobs in Simpang ampat

Design Verification Engineer (SOC/ASIC/Verilog)

Permanent Job

Singapore

3-8 years

7000 - 15000 USD monthly

assembly coding RISC-V Uvm assertion-based verification systemverilog MIPI AMBA DSP cores Semiformal Verification C/C++ Ovm Perl Verilog Shell scripting Arm Python Tcl Systemc

4 days ago

Design Verification Engineer (SOC/ASIC/Verilog)

Permanent Job

Singapore

3-8 years

7000 - 15000 USD monthly

assembly coding RISC-V Uvm assertion-based verification systemverilog MIPI AMBA DSP cores Semiformal Verification C/C++ Ovm Perl Verilog Shell scripting Arm Python Tcl Systemc

4 days ago

Design Verification Engineer (SoC/ASIC/RTL)

Permanent Job

Singapore

3-8 years

7000 - 15000 USD monthly

assembly coding RISC-V Uvm assertion-based verification systemverilog MIPI AMBA DSP cores Semiformal Verification C/C++ Ovm Perl Verilog Shell scripting Arm Python Tcl Systemc

5 days ago

RTL Design Engineer (ASIC/SOC/Digital Design/Verilog/System Verilog)

Permanent Job

Singapore

5-7 years

7000 - 15000 SGD monthly

Designer Microsoft Powerpoint Adobe Creative Suite Reliability Rtl Design Ip systemverilog Adobe After Effects Product Development Electrical Engineering Fpga Adobe Illustrator Vcs Verilog Adobe Photoshop C++

5 days ago

Design Verification Engineer (SOC/ASIC/Verilog)

Permanent Job

Singapore

2-5 years

7000 - 15000 SGD monthly

architects Documentation Skills MIPI Uvm systemverilog Functional Verification ASIC Electrical Engineering Vlsi Perl Tcl Scripting Test Cases Soc Python Verilog

5 days ago

ASIC Physical Design Engineer

Permanent Job

Singapore

2-5 years

4000 - 8000 SGD monthly

Timing Closure Gds synopsys tools Rtl Design Cadence RTL Synthesis Ic Physical Design Static Timing Analysis Scripting Unix Routing Eda Vba Macros Linux

6 days ago

Staff ASIC Physical Design Engineer

Permanent Job

Singapore

5-7 years

7000 - 14000 SGD monthly

Timing Closure Gds synopsys tools Rtl Design Cadence RTL Synthesis Ic Physical Design Static Timing Analysis Scripting Unix Routing Eda Vba Macros Linux

6 days ago

RTL Design Engineer (ASIC/SOC/Digital Design/Verilog/System Verilog)

Permanent Job

Singapore

5-7 years

7000 - 15000 USD monthly

Verdi RTL Digital Design systemverilog RISC AXI protocols pre-layout AMBA APB post-layout simulation Vcs Soc Verilog Arm

4 days ago

Design Verification Engineer (SOC/ASIC/Verilog)

Permanent Job

Singapore

3-8 years

7000 - 15000 USD monthly

assembly coding RISC-V Uvm assertion-based verification systemverilog MIPI AMBA DSP cores Semiformal Verification C/C++ Ovm Perl Verilog Shell scripting Arm Python Tcl Systemc

4 days ago

RTL Design Engineer (ASIC/SOC/Digital Design/Verilog/System Verilog)

Permanent Job

Singapore

5-7 years

7000 - 15000 USD monthly

RTL RISC AMBA APB systemverilog post-layout simulation pre-layout Verdi AXI protocols Digital Design Soc Vcs Verilog Arm

5 days ago

RTL Design Engineer (ASIC/SOC/Digital Design/Verilog/System Verilog)

Permanent Job

Singapore

5-7 years

7000 - 15000 USD monthly

Verdi RTL Digital Design systemverilog RISC AXI protocols pre-layout AMBA APB post-layout simulation Vcs Soc Verilog Arm

4 days ago

RTL Design Engineer (ASIC/SOC/Digital Design/System Verilog/Verilog)

Permanent Job

Singapore

5-7 years

7000 - 15000 USD monthly

Verdi RTL Digital Design systemverilog RISC AXI protocols pre-layout AMBA APB post-layout simulation Vcs Soc Verilog Arm

4 days ago

Staff ASIC Physical Design Engineer

Permanent Job

Singapore

5-7 years

7000 - 14000 USD monthly

Netlist GDS flow Detailed routing Physical Verification Cadence RTL synthesis EDA Tools Placement Siemens Clock Tree Synthesis Synopsys formal verification Timing Analysis UNIX Scripting Languages Linux

4 days ago

ASIC Physical Design Engineer

Permanent Job

Singapore

2-4 years

4000 - 8000 USD monthly

Netlist Detailed routing Physical Verification Cadence RTL synthesis Gds Placement Siemens Clock Tree Synthesis Synopsys formal verification Timing Analysis Eda UNIX Scripting Languages Linux

4 days ago

RTL Design Engineer (ASIC/SOC/Digital Design/Verilog/System Verilog)

Permanent Job

Singapore

5-7 years

7000 - 15000 SGD monthly

10 days ago

Design Verification Engineer (SoC/ASIC/RTL)

Permanent Job

Singapore

2-5 years

7000 - 15000 SGD monthly

architects Documentation Skills MIPI Uvm systemverilog Functional Verification ASIC Electrical Engineering Vlsi Perl Tcl Scripting Test Cases Soc Python Verilog

10 days ago

Design Verification Engineer (SoC/ASIC/RTL)

Permanent Job

Singapore

2-5 years

7000 - 15000 SGD monthly

architects Documentation Skills MIPI Uvm systemverilog Functional Verification ASIC Electrical Engineering Vlsi Perl Tcl Scripting Test Cases Soc Python Verilog

12 days ago

RTL Design Engineer (ASIC/SOC/Digital Design/Verilog/System Verilog)

Permanent Job

Singapore

5-7 years

7000 - 15000 SGD monthly

12 days ago

RTL Design Engineer (ASIC/SOC/Digital Design/Verilog/System Verilog)

Permanent Job

Singapore

5-7 years

7000 - 15000 SGD monthly

17 days ago

RTL Design Engineer (ASIC/SOC/Digital Design)

Permanent Job

Singapore

5-7 years

7000 - 15000 SGD monthly

19 days ago

Design Verification Engineer (SoC/ASIC/RTL)

Permanent Job

Singapore

2-5 years

7000 - 15000 SGD monthly

architects Documentation Skills MIPI Uvm systemverilog Functional Verification ASIC Electrical Engineering Vlsi Perl Tcl Scripting Test Cases Soc Python Verilog

15 days ago

Design Verification Engineer (SOC/ASIC/UVM/OVM)

Permanent Job

Singapore

2-5 years

7000 - 15000 SGD monthly

architects Documentation Skills MIPI Uvm systemverilog Functional Verification ASIC Electrical Engineering Vlsi Perl Tcl Scripting Test Cases Soc Python Verilog

19 days ago

Cryogenic ASIC scientist for quantum technologies (analog/mixed signal and RF) (ICDS), IME

Permanent Job

Singapore

7-10 years

5950 - 11900 SGD monthly

Tape Rf Circuit Design CMOS Analog Circuit Design Publications Team Player Ic Electrical Engineering Analog System Integration integrated circuit design Matlab Python

17 days ago

RTL Design Engineer (ASIC/SOC/Digital Design/Verilog/System Verilog)

Permanent Job

Singapore

5-7 years

7000 - 15000 SGD monthly

15 days ago

Cryogenic ASIC scientist for quantum technologies (analog/mixed signal and RF) (ICDS), IME

Permanent Job

Singapore

5-7 years

5950 - 11900 SGD monthly

Tape Rf Circuit Design CMOS Analog Circuit Design Publications Team Player Ic Electrical Engineering Analog System Integration integrated circuit design Matlab Python

17 days ago

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Asic Jobs in Simpang ampat