Clock Tree Synthesis Jobs

ASIC Physical Design Engineer

Permanent Job

Singapore

2-4 years

4000 - 8000 USD monthly

Netlist Detailed routing Physical Verification Cadence RTL synthesis Gds Placement Siemens Clock Tree Synthesis Synopsys formal verification Timing Analysis Eda UNIX Scripting Languages Linux

8 days ago

Staff ASIC Physical Design Engineer

Permanent Job

Singapore

5-7 years

7000 - 14000 USD monthly

Netlist GDS flow Detailed routing Physical Verification Cadence RTL synthesis EDA Tools Placement Siemens Clock Tree Synthesis Synopsys formal verification Timing Analysis UNIX Scripting Languages Linux

8 days ago

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Clock Tree Synthesis Jobs

ASIC Physical Design Engineer

Staff ASIC Physical Design Engineer