Eda Jobs

EDA Sales Engineer

Permanent Job

Singapore

0-2 years

4000 - 7000 USD monthly

high-speed electronics EMI/EMC Fmea Antenna Root-Cause Analysis high-speed PCB design signal/power integrity rf circuits TRIZ methodologies DOE Optimization Antenna Design Product Design RF system Manufacturing Process electromagnetics theory Six-Sigma

4 days ago

Lead Engineer, Design Verification (IC Chip Design company)

Permanent Job

Singapore

10-15 years

12000 - 15000 SGD monthly

Hardware Documentation Skills Digital Signal Processors Uvm systemverilog Functional Verification ASIC Vlsi Perl Arm Test Cases Eda Soc Flash Debugging Verilog

5 days ago

Staff Engineer, Design Verification

Permanent Job

Singapore

10-15 years

8000 - 12000 SGD monthly

Hardware Architect Documentation Skills Digital Signal Processors systemverilog Functional Verification Product Development Vlsi Perl Arm Test Cases Eda Soc Python Debugging Verilog

5 days ago

Sr /IC Design Engineer (Design Verification)

Permanent Job

Singapore

0-2 years

5000 - 10000 SGD monthly

invention Analytical Skills Digital IC Design Uvm Rtl Design Ip systemverilog Functional Verification ASIC Ic Vlsi Eda Fpga Soc Flash Computer Architecture Debugging Verilog

5 days ago

Sr Design Engineer (Physical Design)

Permanent Job

Singapore

0-2 years

5000 - 10000 SGD monthly

Timing Closure Gds floorplanning Digital IC Design Autocad Dft RTL Synthesis Physical Design Perl Static Timing Analysis Routing Eda Rc

5 days ago

Sr /IC Design Engineer (Design Verification)

Permanent Job

Singapore

0-2 years

5000 - 10000 SGD monthly

invention Analytical Skills Digital IC Design Uvm Rtl Design Ip systemverilog Functional Verification ASIC Ic Vlsi Eda Fpga Soc Flash Computer Architecture Debugging Verilog

5 days ago

Sr Design Engineer (Physical Design)

Permanent Job

Singapore

0-2 years

5000 - 10000 SGD monthly

Timing Closure Gds floorplanning Digital IC Design Autocad Dft RTL Synthesis Physical Design Perl Static Timing Analysis Routing Eda Rc

5 days ago

Full Chip Physical Design Verification CAD Engineer

Permanent Job

Singapore

2-5 years

4800 - 8600 SGD monthly

Physical Verification Design Verification synopsys tools Cadence Cadence Virtuoso Asic verification Ic Teamwork Skills Physical Design Perl Eda Python

5 days ago

Staff Engineer / Technical Manager, Full Chip Physical Design Verification CAD

Permanent Job

Singapore

7-10 years

8000 - 15000 SGD monthly

Physical Verification Design Verification synopsys tools Cadence Validation and Verification Cadence Virtuoso Asic verification Ic Teamwork Skills Physical Design Perl Eda Python

5 days ago

Staff Engineer, Design Verification

Permanent Job

Singapore

7-10 years

8000 - 12000 SGD monthly

Hardware Architect Documentation Skills Digital Signal Processors systemverilog Functional Verification Product Development Vlsi Perl Arm Test Cases Eda Soc Python Debugging Verilog

5 days ago

ASIC Physical Design Engineer

Permanent Job

Singapore

2-5 years

4000 - 8000 SGD monthly

Timing Closure Gds synopsys tools Rtl Design Cadence RTL Synthesis Ic Physical Design Static Timing Analysis Scripting Unix Routing Eda Vba Macros Linux

6 days ago

Staff ASIC Physical Design Engineer

Permanent Job

Singapore

5-7 years

7000 - 14000 SGD monthly

Timing Closure Gds synopsys tools Rtl Design Cadence RTL Synthesis Ic Physical Design Static Timing Analysis Scripting Unix Routing Eda Vba Macros Linux

6 days ago

Senior/Staff Engineer (Design Verification)

Permanent Job

Singapore

0-1 years

4800 - 8600 SGD monthly

Hardware Uvm Ip systemverilog ASIC Team Player Perl Arm Scripting Unix Eda Soc Networking Ethernet Debugging Verilog

5 days ago

Sr Design Engineer (Physical Design)

Permanent Job

Singapore

1-3 years

5000 - 10000 USD monthly

Sta CTS RTL Scan taping out complex SOC deep sub-micron routing issues Dft Production Gds Floor Planning Synthesis DRC/LVS Systems Analog Design backend design EDA tools power and timing rc extraction Synopsys ICC2 timing closure sign-off Static Timing Analysis Applications Route Perl Tcl

4 days ago

Senior (Staff) Physical Design / IC Backend Design Engineer

Permanent Job

Singapore

5-7 years

8000 - 12000 USD monthly

EDA Tools Physical Design Perl Python Tcl

4 days ago

Sr Design Engineer (Physical Design)

Permanent Job

Singapore

1-3 years

5000 - 10000 USD monthly

Synthesis RTL DRC/LVS Scan Systems deep sub-micron routing issues Dft Production Gds Analog Design backend design EDA tools Synopsys ICC2 timing closure sign-off Applications Perl Static Timing Analysis Tcl

4 days ago

Senior / Staff Physical Design Engineer

Permanent Job

Singapore

Fresher

4800 - 8600 USD monthly

floorplanning Cadence Physical Design Timing Closure Electrical Engineering Ic Cadence Virtuoso synopsys tools Eda Debugging Programming Static Timing Analysis

4 days ago

Full Chip Physical Design Verification CAD Engineer

Permanent Job

Singapore

4-6 years

4800 - 8600 USD monthly

physical verification tools EDA (Electronic Design Automation) tools UNIX (Linux) platforms DRC/LVS Physical Design IC manufacturing processes semiconductor device physics Perl Python Tcl

4 days ago

Staff Engineer / Technical Manager, Full Chip Physical Design Verification CAD

Permanent Job

Singapore

8-10 years

8000 - 15000 USD monthly

physical verification tools EDA (Electronic Design Automation) tools UNIX (Linux) platforms DRC/LVS Physical Design IC manufacturing processes semiconductor device physics Perl Python Tcl

4 days ago

Staff ASIC Physical Design Engineer

Permanent Job

Singapore

5-7 years

7000 - 14000 USD monthly

Netlist GDS flow Detailed routing Physical Verification Cadence RTL synthesis EDA Tools Placement Siemens Clock Tree Synthesis Synopsys formal verification Timing Analysis UNIX Scripting Languages Linux

4 days ago

ASIC Physical Design Engineer

Permanent Job

Singapore

2-4 years

4000 - 8000 USD monthly

Netlist Detailed routing Physical Verification Cadence RTL synthesis Gds Placement Siemens Clock Tree Synthesis Synopsys formal verification Timing Analysis Eda UNIX Scripting Languages Linux

4 days ago

Digital Implementation Engineer

Permanent Job

Singapore

0-2 years

EDA Tools Verilog Hdl Interpersonal Skills Digital Design Communication Skills Shell Perl System Verilog Python Tcl

5 days ago

Graduate Engineer, Digital IC Design

Permanent Job

Singapore

0-2 years

communication algorithms cpu design RTL Wireless Communication chip test low-power designs Timing Constraints FPGA prototype verification static-timing analysis Eda Soc System Verilog

11 days ago

Design Verification Engineer

Permanent Job

Singapore

5-7 years

7000 - 10000 SGD monthly

Hardware Documentation Skills Circuit Design Uvm Ip systemverilog Functional Verification ASIC Electronics Vlsi Scripting Eda Fpga Vcs Soc Ethernet Flash Debugging Verilog

9 days ago

Design Verification Engineer

Permanent Job

Singapore

0-1 years

5000 - 8000 SGD monthly

Hardware Documentation Skills Uvm Ip systemverilog Functional Verification ASIC Vlsi Test Cases Eda Fpga Soc Ethernet Flash Debugging Verilog

8 days ago

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Eda Jobs

EDA Sales Engineer

Lead Engineer, Design Verification (IC Chip Design company)

Staff Engineer, Design Verification

Sr /IC Design Engineer (Design Verification)

Sr Design Engineer (Physical Design)

Sr /IC Design Engineer (Design Verification)

Sr Design Engineer (Physical Design)

Full Chip Physical Design Verification CAD Engineer

Staff Engineer / Technical Manager, Full Chip Physical Design Verification CAD

Staff Engineer, Design Verification

ASIC Physical Design Engineer

Staff ASIC Physical Design Engineer

Senior/Staff Engineer (Design Verification)

Sr Design Engineer (Physical Design)

Senior (Staff) Physical Design / IC Backend Design Engineer

Sr Design Engineer (Physical Design)

Senior / Staff Physical Design Engineer

Full Chip Physical Design Verification CAD Engineer

Staff Engineer / Technical Manager, Full Chip Physical Design Verification CAD

Staff ASIC Physical Design Engineer

ASIC Physical Design Engineer

Digital Implementation Engineer

Graduate Engineer, Digital IC Design

Design Verification Engineer

Design Verification Engineer