Fresher Logic Synthesis Jobs

Digital IC Design Engineer (SoC Timing)

Permanent Job

Singapore

0-2 years

Logic Synthesis Dft ASIC Power structure Timing Closure Linux static timing analysis UNIX

14 days ago

Digital IC Design Engineer (SoC Timing)

Permanent Job

Singapore ,

International Business Park

0-2 years

5000 - 8000 USD monthly

ASIC Design Power structure Problem-solving Timing Closure analytical Logic Synthesis Dft UNIX static timing analysis Scripting Linux

8 days ago

Senior Digital IC Design Engineer

Permanent Job

Singapore ,

International Business Park

0-2 years

7000 - 12000 USD monthly

ASIC Design RTL gate-level simulation analytical Logic Synthesis RTL Coding communication Problem-solving Interpersonal Timing Closure Verification Dft UNIX Scripting Linux static timing analysis

8 days ago

Digital ASIC Designer

Permanent Job

Singapore

0-2 years

power analysis logic equivalent check digital circuit design Logic Synthesis VHDL ASIC Embedded Systems baseband signal processing static timing analysis Networking Verilog Computer Architecture

a month ago

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Fresher Logic Synthesis Jobs

Digital IC Design Engineer (SoC Timing)

Digital IC Design Engineer (SoC Timing)

Senior Digital IC Design Engineer

Digital ASIC Designer