Logic Synthesis Jobs

Senior Digital IC Design Engineer

Permanent Job

Singapore

0-2 years

7000 - 12000 USD monthly

analytical RTL gate-level simulation Interpersonal Problem-solving Logic Synthesis Dft ASIC Design RTL Coding Timing Closure Verification communication static timing analysis UNIX Linux Scripting

4 days ago

Digital IC Design Engineer (SoC Timing)

Permanent Job

Singapore

0-2 years

5000 - 8000 USD monthly

Logic Synthesis Dft Power structure analytical ASIC Design Timing Closure Problem-solving static timing analysis Linux UNIX Scripting

4 days ago

Digital IC Design Engineer (SoC Timing)

Permanent Job

Singapore

0-2 years

Logic Synthesis Dft ASIC Power structure Timing Closure Linux static timing analysis UNIX

11 days ago

Digital ASIC Designer

Permanent Job

Singapore

0-2 years

power analysis logic equivalent check digital circuit design Logic Synthesis VHDL ASIC Embedded Systems baseband signal processing static timing analysis Networking Verilog Computer Architecture

30 days ago

micro-architecture design digital ic design Synthesis digital MAC/baseband/high-speed interfaces Timing SOC system architecture/block definitions GNSS Cadence RTL Coding RTL logic design Power area analysis Synopsis tools DSP design WiFi Bluetooth static timing analysis Cpu Verilog Bluetooth Low Energy System Verilog

26 days ago

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Logic Synthesis Jobs

Senior Digital IC Design Engineer

Digital IC Design Engineer (SoC Timing)

Digital IC Design Engineer (SoC Timing)

Digital ASIC Designer

Semiconductor Design Engineer