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26
Synopsys Jobs
ASIC Physical Design Engineer
Avago Technologies International Sales Pte. Limited
Permanent Job
Singapore
2-5 years
4000 - 8000 SGD monthly
Timing Closure
Gds
synopsys tools
Rtl Design
Cadence
RTL Synthesis
Ic
Physical Design
Static Timing Analysis
Scripting
Unix
Routing
Eda
Vba Macros
Linux
6 days ago
Staff ASIC Physical Design Engineer
Avago Technologies International Sales Pte. Limited
Permanent Job
Singapore
5-7 years
7000 - 14000 SGD monthly
Timing Closure
Gds
synopsys tools
Rtl Design
Cadence
RTL Synthesis
Ic
Physical Design
Static Timing Analysis
Scripting
Unix
Routing
Eda
Vba Macros
Linux
6 days ago
Full Chip Physical Design Verification CAD Engineer
Mediamonks Singapore Pte. Ltd.
Permanent Job
Singapore
2-5 years
4800 - 8600 SGD monthly
Physical Verification
Design Verification
synopsys tools
Cadence
Cadence Virtuoso
Asic verification
Ic
Teamwork Skills
Physical Design
Perl
Eda
Python
5 days ago
Electronic Software Engineer
BUSINESS EDGE PERSONNEL SERVICES PTE LTD
Permanent Job
Singapore
0-2 years
2800 - 3000 USD monthly
Embedded System
Network communication
Synopsys
C/C++
Linux Os
Verilog
Python
4 days ago
Senior/Staff Engineer (Design Verification)
MEDIATEK SINGAPORE PTE. LTD.
Permanent Job
Singapore
0-2 years
4800 - 8600 USD monthly
Mentor Simulator
Cshell
Cadence
Uvm
Synopsys
systemverilog
Perl
Makefile
UNIX
Python
4 days ago
IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design)
HKM HR MANAGEMENT PTE. LTD.
Permanent Job
Singapore
2-4 years
7000 - 15000 USD monthly
advanced CMOS processes
Cadence
silicon failures
Mentor Graphics Tools
Analog Circuit Design
digital IC design
Design
RTL Coding
design improvements
Verification
customer needs
Digital
circuit simulations
tape-out
Analysis
circuit solutions
development of design methodologies
Floor Planning
Layout
fundamental theories
inventive designs
mixed-signal
IC development flow
Synopsys
cross-functional teams
Test Plans
Analog
4 days ago
IC Design Engineer (Semiconductor Front-End Design/Digital IC Design/Analog /Mixed-Signal)
HKM HR MANAGEMENT PTE. LTD.
Permanent Job
Singapore
2-4 years
7000 - 15000 USD monthly
circuit solutions
Analysis
cross-functional teams
RTL Coding
circuit simulations
Cadence
customer needs
tape-out
inventive designs
Verification
advanced CMOS processes
IC development flow
Synopsys
Floor Planning
Mentor Graphics Tools
Analog Circuit Design
Digital
Layout
silicon failures
Design
design improvements
fundamental theories
development of design methodologies
mixed-signal
digital IC design
Analog
Test Plans
5 days ago
IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design/Mixed-Signal)
HKM HR MANAGEMENT PTE. LTD.
Permanent Job
Singapore
2-4 years
7000 - 15000 USD monthly
advanced CMOS processes
Cadence
silicon failures
Mentor Graphics Tools
Analog Circuit Design
digital IC design
Design
RTL Coding
design improvements
Verification
customer needs
Digital
circuit simulations
tape-out
Analysis
circuit solutions
development of design methodologies
Floor Planning
Layout
fundamental theories
inventive designs
mixed-signal
IC development flow
Synopsys
cross-functional teams
Test Plans
Analog
4 days ago
Senior / Staff Physical Design Engineer
MEDIATEK SINGAPORE PTE. LTD.
Permanent Job
Singapore
Fresher
4800 - 8600 USD monthly
floorplanning
Cadence
Physical Design
Timing Closure
Electrical Engineering
Ic
Cadence Virtuoso
synopsys tools
Eda
Debugging
Programming
Static Timing Analysis
4 days ago
Design Verification Engineer
BITSILICA PTE. LTD.
Permanent Job
Singapore
5-7 years
7000 - 10000 USD monthly
Cadence IUS
IP Verification
Uvm
UPF
GPT
ISO7816
LPDDR2
Verdi
WDT
Verification
Synopsys VCS
CFDM
Axi
AGPT
APB
C-shell
AHB
Fpga
C
Soc
Spi
Jtag
Pcie
Verilog
System Verilog
C++
Automation
Gpio
Perl
Ddr3
4 days ago
Sr Design Engineer (Physical Design)
ETHOS TECH ONE PTE. LTD.
Permanent Job
Singapore
1-3 years
5000 - 10000 USD monthly
Synthesis
RTL
DRC/LVS
Scan
Systems
deep sub-micron routing issues
Dft
Production
Gds
Analog Design
backend design EDA tools
Synopsys ICC2
timing closure sign-off
Applications
Perl
Static Timing Analysis
Tcl
4 days ago
Sr Design Engineer (Physical Design)
ETHOS SEARCH ASSOCIATES PTE. LTD.
Permanent Job
Singapore
1-3 years
5000 - 10000 USD monthly
Sta
CTS
RTL
Scan
taping out complex SOC
deep sub-micron routing issues
Dft
Production
Gds
Floor Planning
Synthesis
DRC/LVS
Systems
Analog Design
backend design EDA tools
power and timing
rc extraction
Synopsys ICC2
timing closure sign-off
Static Timing Analysis
Applications
Route
Perl
Tcl
4 days ago
ASIC Physical Design Engineer
AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Permanent Job
Singapore
2-4 years
4000 - 8000 USD monthly
Netlist
Detailed routing
Physical Verification
Cadence
RTL synthesis
Gds
Placement
Siemens
Clock Tree Synthesis
Synopsys
formal verification
Timing Analysis
Eda
UNIX
Scripting Languages
Linux
4 days ago
Staff ASIC Physical Design Engineer
AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Permanent Job
Singapore
5-7 years
7000 - 14000 USD monthly
Netlist
GDS flow
Detailed routing
Physical Verification
Cadence
RTL synthesis
EDA Tools
Placement
Siemens
Clock Tree Synthesis
Synopsys
formal verification
Timing Analysis
UNIX
Scripting Languages
Linux
4 days ago
DFT/MBIST Engineer for Advanced Process Node & Package Technology
MEDIATEK SINGAPORE PTE. LTD.
Permanent Job
Singapore
4-6 years
4800 - 8600 USD monthly
Dft
MBIST
Synopsys
PFA
RTL
Sram
English
Mentor
Tcl
Python
Perl
Hdl
5 days ago
Staff Engineer/Technical Manager - DFT/MBIST for Advanced Process Node & Package Technology
MEDIATEK SINGAPORE PTE. LTD.
Permanent Job
Singapore
7-9 years
8000 - 15000 USD monthly
Synopsys
physical failure analysis
Mentor
Rtl Design
Tcl
Python
Perl
5 days ago
Electronics Engineer (Embedded / Linux / Software Design / C/C++ / North)
TRUST RECRUIT PTE. LTD.
Permanent Job
Singapore
1-2 years
3500 - 4500 USD monthly
Embedded System
Network communication
Synopsys
C/C++
Linux Os
Verilog
Python
4 days ago
Analog Layout Senior/Staff Engineer
MARVELL ASIA PTE LTD
Permanent Job
Singapore
3-5 years
5900 - 9500 USD monthly
Skill
layout methodology
ERC
Cadence
Ample
CALIBRE DRC
LVS
Synopsys
Perl
4 days ago
IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design/Mixed-Signal)
HKM HR MANAGEMENT PTE. LTD.
Permanent Job
Singapore
2-4 years
7000 - 15000 USD monthly
advanced CMOS processes
Cadence
silicon failures
Mentor Graphics Tools
Analog Circuit Design
digital IC design
Design
RTL Coding
design improvements
Verification
customer needs
Digital
circuit simulations
tape-out
Analysis
circuit solutions
development of design methodologies
Floor Planning
Layout
fundamental theories
inventive designs
mixed-signal
IC development flow
Synopsys
cross-functional teams
Test Plans
Analog
4 days ago
Physical Design Engineer
BITSILICA PTE. LTD.
Permanent Job
Singapore
5-7 years
7000 - 10000 USD monthly
Hierarchical partitioning
CTS
PnR tools
Synopsys ICC
Netlist
Cadence Innovus
GDSII
low power designs
Tcl Scripting
4 days ago
Electronics Engineer
TEAM ONE TECHNOLOGIES PTE LTD
Permanent Job
Singapore
0-2 years
2800 - 3300 USD monthly
Network communication
Synopsys
C/C++ programming
Embedded System
Linux Os
Verilog
Python
5 days ago
Staff Engineer / Technical Manager, Full Chip Physical Design Verification CAD
Mediamonks Singapore Pte. Ltd.
Permanent Job
Singapore
7-10 years
8000 - 15000 SGD monthly
Physical Verification
Design Verification
synopsys tools
Cadence
Validation and Verification
Cadence Virtuoso
Asic verification
Ic
Teamwork Skills
Physical Design
Perl
Eda
Python
5 days ago
Principal DFT Engineer
MaxLinear
Permanent Job
Singapore
15-17 years
OCC controller
Synthesis
script writing
Synopsys SMS
VLSI RTL2GDSII design flow
MBIST
DFT advisor
Mentors SSN
boundary scan
DFT Compiler
ATPG Scan
constraining
Test Kompress
high level programming
static timing analysis
Hdl
21 days ago
[2025 Campus Hire] NPU Physical Design Engineer
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Permanent Job
Singapore
5-7 years
primetime
Tweaker
Synopsys ICC2/FC
Ip
Cadence Innovus
RTL
Tempus
PrimeClosure
Voltus
redhawk
Gds
custom circuit design
Scripting
29 days ago
CAD Software Engineer
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Permanent Job
Singapore
0-2 years
Physical Verification EDA tools
Web Application Framework
CAD flow automation
Cadence Virtuoso
Synopsys Laker
Siemens Calibre DesignRev
Javascript
Perl
Python
Tcl
29 days ago
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