Timing Jobs

IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design/Mixed-Signal)

Permanent Job

Singapore

2-5 years

7000 - 15000 SGD monthly

Timing Closure CMOS Analog Circuit Design Cadence simulations ASIC Graphics Ic Teamwork Skills Electrical Engineering Layout silicon Analog Wireless Soc Debugging

15 days ago

Construction Supervisor

Permanent Job

Singapore

2-5 years

2900 - 4000 SGD monthly

Coaching Budgets Construction Timing Closure Site Management Counseling Drawing Electrical Project timings Compliance Attention To Details Carpentry Scheduling Cost Control

18 days ago

Senior / Staff Physical Design Engineer

Permanent Job

Singapore

0-1 years

4800 - 8600 SGD monthly

Factory Timing Closure floorplanning Ic Physical Design Electrical Engineering Static Timing Analysis Eda Neural network Debugging

17 days ago

IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design)

Permanent Job

Singapore

2-5 years

7000 - 15000 SGD monthly

Timing Closure CMOS Analog Circuit Design Cadence simulations ASIC Graphics Ic Teamwork Skills Electrical Engineering Layout silicon Analog Wireless Soc Debugging

19 days ago

Staff Engineer - Development (Instrument Architecture)

Permanent Job

Singapore

3-5 years

Reliability Life Tests Runtime Models Root Cause Analysis Performance Models COGS Models design of experiments Biochemistry Workflows Scientific Computing Presentation Skills System Models Assembly Process Workflows Effective Communication R SNR Models Hardware Timing Diagrams System Tolerance Budgets Simulation MATLAB Python

21 days ago

Principal DFT Engineer

Permanent Job

Singapore

15-17 years

OCC controller Synthesis script writing Synopsys SMS VLSI RTL2GDSII design flow MBIST DFT advisor Mentors SSN boundary scan DFT Compiler ATPG Scan constraining Test Kompress high level programming static timing analysis Hdl

21 days ago

Front-end design (RTL) Lead Research Engineer Heterogeneous Chiplet Systems, IME

Permanent Job

Singapore

0-2 years

power analysis Timing Analysis RTL Implementation Verilog/SystemVerilog System Level Architecture Modeling Digital IC Design Eda Fpga Matlab

16 days ago

Senior Manager , Serdes Analog Design

Permanent Job

Singapore

10-15 years

12000 - 15000 SGD monthly

Problem Solving CMOS Cadence Virtuoso Team Building Skills Ic Static Timing Analysis Analog analog circuits Sata Debugging

23 days ago

Serdes Analog Design Engineer

Permanent Job

Singapore

2-5 years

8000 - 12000 SGD monthly

ADCs Problem Solving Circuit Design Communication Skills ASIC Cadence Virtuoso Static Timing Analysis analog circuits Eda Debugging

23 days ago

IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design/Mixed-Signal)

Permanent Job

Singapore

2-5 years

7000 - 15000 SGD monthly

Timing Closure CMOS Analog Circuit Design Cadence simulations ASIC Graphics Ic Teamwork Skills Electrical Engineering Layout silicon Analog Wireless Soc Debugging

22 days ago

IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design/Mixed-Signal)

Permanent Job

Singapore

2-5 years

7000 - 15000 SGD monthly

Timing Closure CMOS Analog Circuit Design Cadence simulations ASIC Graphics Ic Teamwork Skills Electrical Engineering Layout silicon Analog Wireless Soc Debugging

26 days ago

Administrative And Support Staff

Permanent Job

Singapore

0-2 years

reviews calling flexible timing Team Player updates

27 days ago

IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design/Mixed-Signal)

Permanent Job

Singapore

2-5 years

7000 - 15000 SGD monthly

Timing Closure CMOS Analog Circuit Design Cadence simulations ASIC Graphics Ic Teamwork Skills Electrical Engineering Layout silicon Analog Wireless Soc Debugging

24 days ago

Semiconductor Design Engineer

Permanent Job

Singapore

5-7 years

micro-architecture design digital ic design Synthesis digital MAC/baseband/high-speed interfaces Timing SOC system architecture/block definitions GNSS Cadence RTL Coding RTL logic design Power area analysis Synopsis tools DSP design WiFi Bluetooth static timing analysis Cpu Verilog Bluetooth Low Energy System Verilog

26 days ago

Front-end design (RTL) Scientist for Heterogeneous Chiplet Systems, IME

Permanent Job

Singapore

0-2 years

power analysis Timing Analysis RTL Implementation Verilog/SystemVerilog System Level Architecture Modeling Digital IC Design Eda Fpga Matlab

26 days ago

Front-end design (RTL) Scientist for Heterogeneous Chiplet Systems, IME

Permanent Job

Singapore

0-2 years

power analysis Timing Analysis RTL Implementation Verilog/SystemVerilog System Level Architecture Modeling Digital IC Design Eda Fpga Matlab

26 days ago

Foundation IP Design Engineer

Permanent Job

Singapore

0-2 years

memory circuit design chip level integration timing diagrams signal integrity analysis EM/IR analysis process technology behavioral and physical memory models multi-tasking transistor level simulators silicon Interpersonal logic cells custom macros memory compilers DFT schemes circuit behavior Leadership Skills Reliability Analysis silicon test plan communication automation scripts device physics

30 days ago

Digital ASIC Designer

Permanent Job

Singapore

0-2 years

power analysis logic equivalent check digital circuit design Logic Synthesis VHDL ASIC Embedded Systems baseband signal processing static timing analysis Networking Verilog Computer Architecture

30 days ago

Regional Procurement Manager (Marketing Category)

Permanent Job

Singapore

Fresher

Procurement Market Research Business Allocation Policies Negotiation Compliance Risk Assessment Sourcing Project Timing Forecasts Deal with Ambiguity Catalog Buying P2P Conflict Management Supplier Performance Management Creative Production Supplier Management Category Intelligence influencer marketing Stakeholder Management Communication Contracts People Management Corporate Communication Change Management

30 days ago

Staff/Sr. SoC Design Engineer

Permanent Job

Singapore

0-2 years

System Modelling secured system Timing Analysis systemverilog video analytics RTL Coding always-on system RISC processor system neural processing general programming Automotive system bus interconnect area analysis assembly code programming power analysis Simulation Soc Architecture Emulator Verilog Tcl Arm Perl Embedded C Systemc Video Processing Python Bash Scripting Languages

a month ago

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Timing Jobs

IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design/Mixed-Signal)

Construction Supervisor

Senior / Staff Physical Design Engineer

IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design)

Staff Engineer - Development (Instrument Architecture)

Principal DFT Engineer

Front-end design (RTL) Lead Research Engineer Heterogeneous Chiplet Systems, IME

Senior Manager , Serdes Analog Design

Serdes Analog Design Engineer

IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design/Mixed-Signal)

IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design/Mixed-Signal)

Administrative And Support Staff

IC Design Engineer (Semiconductor/IC Development Flow/Analog Circuit Design/Mixed-Signal)

Semiconductor Design Engineer

Front-end design (RTL) Scientist for Heterogeneous Chiplet Systems, IME

Front-end design (RTL) Scientist for Heterogeneous Chiplet Systems, IME

Foundation IP Design Engineer

Digital ASIC Designer

Regional Procurement Manager (Marketing Category)

Staff/Sr. SoC Design Engineer