Virtuoso Jobs

Full Chip Physical Design Verification CAD Engineer

Permanent Job

Singapore

2-5 years

4800 - 8600 SGD monthly

Physical Verification Design Verification synopsys tools Cadence Cadence Virtuoso Asic verification Ic Teamwork Skills Physical Design Perl Eda Python

5 days ago

Staff Engineer / Technical Manager, Full Chip Physical Design Verification CAD

Permanent Job

Singapore

7-10 years

8000 - 15000 SGD monthly

Physical Verification Design Verification synopsys tools Cadence Validation and Verification Cadence Virtuoso Asic verification Ic Teamwork Skills Physical Design Perl Eda Python

5 days ago

Senior / Staff Physical Design Engineer

Permanent Job

Singapore

Fresher

4800 - 8600 USD monthly

floorplanning Cadence Physical Design Timing Closure Electrical Engineering Ic Cadence Virtuoso synopsys tools Eda Debugging Programming Static Timing Analysis

4 days ago

IC Layout Engineer

Permanent Job

Singapore

2-5 years

2800 - 4000 SGD monthly

Visual Effects Schematic PCB Layout Design Cadence Virtuoso Universal Server Cadence Virtuoso Layout schematic capture Analog cadence spectre

17 days ago

CAD Software Engineer

Permanent Job

Singapore

0-2 years

Physical Verification EDA tools Web Application Framework CAD flow automation Cadence Virtuoso Synopsys Laker Siemens Calibre DesignRev Javascript Perl Python Tcl

29 days ago

Senior Manager , Serdes Analog Design

Permanent Job

Singapore

10-15 years

12000 - 15000 SGD monthly

Problem Solving CMOS Cadence Virtuoso Team Building Skills Ic Static Timing Analysis Analog analog circuits Sata Debugging

23 days ago

Analog IC Design Engineer

Permanent Job

Singapore

2-5 years

5000 - 9000 SGD monthly

Ability To Work Independently Mixed-Signal IC Design Mixed Signal CMOS Analog Circuit Design Cadence Cadence Virtuoso Ic Layout Analog analog circuits integrated circuit design

24 days ago

Serdes Analog Design Engineer

Permanent Job

Singapore

2-5 years

8000 - 12000 SGD monthly

ADCs Problem Solving Circuit Design Communication Skills ASIC Cadence Virtuoso Static Timing Analysis analog circuits Eda Debugging

23 days ago

Cadence Virtuoso manufacturing Foundry Calibre multiple processes Leadership Presentation floorplan blocks SKILLCAD analog structures Project Planning Powerpoint Integrated circuits Policies Layout XL design rules layout data assembly documentation Verification design engineering training instructions project management Word communication wireless consumer electronic products analog and integrated circuits Presentations Latchup prevention ESD protection schemes P&R methods analog layout practices Electrical Engineering Mentoring analog integrated circuits Methodologies Outlook Unix Excel

a month ago

Standard Cell Library Design Engineer

Permanent Job

Singapore

12-14 years

Circuit FinFet Digital Tools RTL Cadence Skill Technology Process Design Gds virtuoso mixed-signal Unix Eda Perl programming Python Tcl

30 days ago

Standard Cell Library Design Engineer

Permanent Job

Singapore

5-7 years

Sta Circuit lib Digital Cadence cell lef Layout Skill physical PNR Design virtuoso mixed-signal Knowledge Unix Eda Verilog Perl programming Scripting Python Tcl

30 days ago

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Virtuoso Jobs

Full Chip Physical Design Verification CAD Engineer

Staff Engineer / Technical Manager, Full Chip Physical Design Verification CAD

Senior / Staff Physical Design Engineer

IC Layout Engineer

CAD Software Engineer

Senior Manager , Serdes Analog Design

Analog IC Design Engineer

Serdes Analog Design Engineer

Principal Layout Designer

Standard Cell Library Design Engineer

Standard Cell Library Design Engineer