Skills and responsibilities:
- Utilize commercial and in-house EDA tools (e.g. Synopsys, Cadence, Siemens) for the design and implementation of 100 400 million gate integrated circuits in 7nm/5nm/3nm/2nm process technologies.
- Proficient with a full Netlist/Gates to GDS flow, inclusive of all construction stages (e.g. RTL synthesis, placement, clock tree synthesis, detailed routing, physical verification, formal verification and timing analysis) for complex digital blocks of up to 12Mgates/3M instances with embedded macros. Ability to handle multiple block assignments in parallel is required.
- Proficiency in UNIX/Linux and scripting languages is advantageous.
Required Qualifications:
- Degree, Masters or PhD in Electrical/Electronics/Computer engineering.
- Minimum of 5 years or more experience in a relevant field.
